Design properties are used during implementation and therefore the configuration related options (CONFIG_MODE, CONFIG_VOLTAGE, and CFGBVS in UltraScale FPGAs) are important to set before bitstreams are generated. CONFIG_MODE specifies the planned configuration mode selection to be defined by the mode pins, CONFIG_VOLTAGE defines the planned configuration interface voltage level on VCCO_0 (and VCCO_65 when used), and CFGBVS defines whether the CFGBVS pin in UltraScale FPGAs is tied to VCCO or GND. See Configuration Banks Voltage Select (Kintex UltraScale and Virtex UltraScale FPGAs) for more information on these features. Refer to the Vivado Design Suite Properties Reference Guide (UG912) for more details on how to define these design properties.