Control Register 0 (00101) - Control Register 0 (00101)

Control Register 0 (00101) - Control Register 0 (00101) - UG570

UltraScale Architecture Configuration User Guide (UG570)

Document ID

UG570

Release Date

2025-03-04

Revision

1.20.1 English

Control register 0 (CTL0) is used to configure the device. Writes to the CTL0 register are masked by the value in the MASK register (this allows the GTS_USR_B signal to be toggled without respecifying the SBITS and PERSIST bits). The name of each bit position in the CTL0 register is given in the following table and described in the subsequent table.

Table 1. Control Register 0 (CTL0)
Description	EFUSE_KEY	ICAP_SELECT	Reserved																	OverTempShutDown	Reserved	ConfigFallback	Reserved	GLUTMASK_B	Reserved	DEC	SBITS[1:0]		PERSIST	Reserved		GTS_USR_B
Bit Index	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Value	0	0	x	x	x	x	x	x	x	x	x	x	x	x	x	x	x	x	x	0	x	0	x	1	0	0	0	0	0	x	x	1

Table 2. Control Register 0 Description
Name	Bit Index	Description
EFUSE_KEY	31	Selects the AES key source: `0`: Battery-backed RAM (default) `1`: eFUSE This bit is internally latched again when DEC is set. It cannot change after that to prevent switching of key sources, although this bit can still be read/write.
ICAP_SELECT	30	ICAPE3 port select: `0`: Top ICAPE3 port enabled (default) `1`: Bottom ICAPE3 port enabled
OverTempShutDown	12	Enables the System Monitor over-temperature shutdown: `0`: Disables over-temperature shutdown (default) `1`: Enables over-temperature shutdown
ConfigFallback	10	Stops when configuration fails and disables fallback to the default bitstream. The bitstream generator option is ConfigFallback: Enable/Disable. `0`: Enables fallback (default) `1`: Disables fallback
GLUTMASK_B	8	Global LUT mask signal. Masks any changeable memory cell readback value. `0`: Masks changeable memory cell readback value, such as distributed RAM or SRL `1`: Does not mask changeable memory cell readback values (default)
DEC	6	AES decryptor enable bit: `0`: Decryptor disabled (default) `1`: Decryptor enabled
SBITS[1:0]	[5:4]	Security level. The FPGA security level is extended to encrypted bitstreams. It is applicable to the configuration port, not to ICAPE3. The security level takes affect at the end of the encrypted bitstream or after EOS for an unencrypted bitstream. `00`: Read/write OK (default) `01`: Readback disabled `1x`: Both writes and reads disabled Only FAR and FDRI allow encrypt write access for security levels `00` and `01` .
PERSIST	3	The configuration interface defined by M2:M0 remains after configuration. Typically used only with the SelectMAP interface to allow reconfiguration and readback. See SelectMAP Configuration Modes. `0`: No (default) `1`: Yes
GTS_USR_B	0	Active-Low global 3-state I/Os. Turns off pull-ups if GTS_CFG_B is also asserted. `0`: I/Os 3-stated `1`: I/Os active (default)