Continuous SelectMAP Data Loading - Continuous SelectMAP Data Loading - UG570

Continuous data loading is used in applications where the configuration controller can provide an uninterrupted stream of configuration data. After power-up, the configuration controller sets the RDWR_B signal for write control (RDWR_B = 0) and asserts the CSI_B signal (CSI_B = 0). RDWR_B must be driven Low before CSI_B is asserted, otherwise an ABORT occurs on the next CCLK.

On the next rising CCLK edge, the device begins sampling the data pins. Only D[07:00] are sampled by configuration until the bus width is determined. After bus width is determined, the proper width of the data bus is sampled for the Synchronization word search. Configuration begins after the synchronization word is clocked into the device.

After the configuration bitstream is loaded, the device enters the startup sequence. The device asserts its DONE signal High in the phase of the startup sequence that is specified by the bitstream. The configuration controller should continue sending CCLK pulses until after the startup sequence has finished. This can require several CCLK pulses after DONE goes High. A conservative number for the clock cycles required after DONE is 64; this will account for the most common use cases. See Clocking to End of Start-up for additional detail.

After configuration, the CSI_B and RDWR_B signals can be de-asserted, or they can remain asserted. Because the SelectMAP port is inactive, toggling RDWR_B at this time does not cause an ABORT. The following figure summarizes the timing of SelectMAP configuration with continuous data loading.

Notes relevant to the previous figure:

1. CSI_B signal can be tied Low if there is only one device on the SelectMAP bus. If CSI_B is not tied Low, it can be asserted at any time.
2. RDWR_B can be tied Low if readback is not needed. RDWR_B should not be toggled after CSI_B has been asserted because this triggers an ABORT on the next CCLK.
3. The Mode pins are sampled when INIT_B goes High.
4. RDWR_B should be asserted before CSI_B to avoid causing an ABORT on the next CCLK.
5. CSI_B is asserted, enabling the SelectMAP interface.
6. The first byte is loaded on the first rising CCLK edge after CSI_B is asserted.
7. The configuration bitstream is loaded one byte per rising CCLK edge.
8. After the startup command is loaded, the device enters the startup sequence.
9. The startup sequence lasts a minimum of eight CCLK cycles.
10. The DONE pin goes High during the startup sequence. Additional CCLKs can be required to complete the startup sequence.
11. After configuration has finished, the CSI_B signal can be deasserted.
12. After the CSI_B signal is deasserted, RDWR_B can be deasserted.
13. The data bus can be x8, x16, or x32 (for slave SelectMAP).