There is a common sequence to be
followed for the FPGA power-up, described in detail in Configuration Details. Special options can require
modifications to the default sequence. For example, when an
MMCM is used, the "MMCM lock" option might need to
be used to wait for the MMCM to lock before beginning
configuration. There are also the "Wait for PLL" or "DCI match" options. If
any of these options are used, then ensure the images in the configuration
source are properly spaced for MultiBoot images. Also, when using slave
modes or the master mode EMCCLK option, ensure enough clock
cycles are supplied to complete the start-up sequence.
If you do not clock the start-up completely, some of the following symptoms can be observed:
- I/O remains disabled
- Multi-function configuration and I/O pins operate in LVCMOS rather than the specified I/O standard.
- ICAP interface cannot be accessed from the FPGA logic because the configuration logic is locked
- This will occur if the device has not reached
the end of start-up state. The device can be fully
operational before the device reaches this end of start-up
state. This can lead to ICAP read and write failures or
multi-function pins not operating in the correct I/O
standard. This event is indicated by the EOS signal being
driven High. This can be observed in the STATUS register or
detected in the FPGA using the STARTUPE3 primitive.
For designs accessing the ICAP, it is good design practice to instantiate the STARTUPE3 primitive. This primitive has an EOS pin, which will indicate when the configuration process has completed and the ICAP is available for read and write access.