Configuration Registers - Configuration Registers

Configuration Registers - Configuration Registers - UG570

UltraScale Architecture Configuration User Guide (UG570)

Document ID

UG570

Release Date

2025-03-04

Revision

1.20.1 English

The following table summarizes the Type 1 packet registers. A detailed explanation of selected registers follows.

Table 1. Type 1 Packet Registers
Name	Read/Write	Address	Description
CRC	Read/Write	`00000`	CRC register.
FAR	Read/Write	`00001`	Frame address register.
FDRI	Write	`00010`	Frame data register, input register (write configuration data).
FDRO	Read	`00011`	Frame data register, output register (read configuration data).
CMD	Read/Write	`00100`	Command register.
CTL0	Read/Write	`00101`	Control register 0.
MASK	Read/Write	`00110`	Masking register for CTL0 and CTL1.
STAT	Read	`00111`	Status register.
LOUT	Write	`01000`	Legacy output register for daisy chain.
COR0	Read/Write	`01001`	Configuration option register 0.
MFWR	Write	`01010`	Multiple frame write register.
CBC	Write	`01011`	Initial CBC value register.
IDCODE	Read/Write	`01100`	Device ID register.
AXSS	Read/Write	`01101`	User access register.
COR1	Read/Write	`01110`	Configuration option register 1.
WBSTAR	Read/Write	`10000`	Warm boot start address register.
TIMER	Read/Write	`10001`	Watchdog timer register.
BOOTSTS	Read	`10110`	Boot history status register.
CTL1	Read/Write	`11000`	Control register 1.
BSPI	Read/Write	`11111`	BPI/SPI configuration options register.