Configuration Pins - Configuration Pins - UG570

UltraScale Architecture Configuration User Guide (UG570)
Document ID
UG570
Release Date
2025-03-04
Revision
1.20.1 English

Each configuration mode has a corresponding set of interface pins that span one or two banks on the FPGA. Bank 0 contains the dedicated configuration pins and is always part of every configuration interface. Bank 65 contains multi-function pins that are involved in a few of the configuration modes. If the Persist option is used (see Persist Option), the multi-function I/O for the selected configuration mode remain active after configuration. The following tables show the configuration pins and their locations across the I/O banks. See Differences Between UltraScale FPGA Families.

Table 1. Configuration Pins - Serial Modes
Pin Name Bank JTAG (Only) Master SPI Slave Serial Master Serial
x1 x2 x4 x8

(dual x4)
POR_OVERRIDE N/A POR_OVERRIDE POR_OVERRIDE POR_OVERRIDE POR_OVERRIDE POR_OVERRIDE POR_OVERRIDE

POR_OVERRIDE
VBATT N/A VBATT VBATT VBATT VBATT VBATT VBATT VBATT
CFGBVS 1 0 CFGBVS CFGBVS CFGBVS CFGBVS CFGBVS CFGBVS CFGBVS
M[2:0] 0 M[2:0]=101 M[2:0]=001 M[2:0]=001 M[2:0]=001 M[2:0]=001 M[2:0]=111 M[2:0]=000
TCK 0 TCK TCK TCK TCK TCK TCK TCK
TMS 0 TMS TMS TMS TMS TMS TMS TMS
TDI 0 TDI TDI TDI TDI TDI TDI TDI
TDO 0 TDO TDO TDO TDO TDO TDO TDO
PROGRAM_B 0 PROGRAM_B PROGRAM_B PROGRAM_B PROGRAM_B PROGRAM_B PROGRAM_B PROGRAM_B
INIT_B 0 INIT_B INIT_B INIT_B INIT_B INIT_B INIT_B INIT_B
DONE 0 DONE DONE DONE DONE DONE DONE DONE
CCLK 0 CCLK CCLK CCLK CCLK CCLK CCLK CCLK
PUDC_B 2 0 PUDC_B 2 PUDC_B 2 PUDC_B 2 PUDC_B 2 PUDC_B 2 PUDC_B 2 PUDC_B 2
RDWR_FCS_B 0 - FCS_B FCS_B FCS_B FCS_B - -
D00_MOSI 0 - MOSI D00_MOSI D00_MOSI D00_MOSI - -
D01_DIN 0 - DIN D01_DIN D01_DIN D01_DIN DIN DIN
D02 0 - - - D02 D02 - -
D03 0 - - - D03 D03 - -
D[07:04] 65 - - - - D[07:04] - -
D[15:08] 65 - - - - - - -
A[15:00]_D[31:16] 65 - - - - - - -
A[28:16] 65 - - - - - - -
EMCCLK 3 65 - EMCCLK 3 EMCCLK 3 EMCCLK 3 EMCCLK 3 - EMCCLK 3
CSI_ADV_B 65 - - - - - - -
DOUT_CSO_B 4 5 65 - DOUT 4 - - - DOUT 4 DOUT 4
FOE_B 65 - - - - - - -
FWE_FCS2_B 65 - - - - FCS2_B - -
RS0, RS1 6 65 - - - - - - -
  1. CFGBVS is available in UltraScale FPGAs only.
  2. PUDC_B has special functionality during configuration but is independent of all configuration interfaces, that is, PUDC_B does not need to be voltage compatible with other pins in a configuration interface.
  3. EMCCLK is only used when the external master CCLK enable option enables EMCCLK as an input for clocking the master configuration modes.
  4. DOUT is only used in a serial configuration daisy-chain for outputting data to the downstream FPGA (or for the Debug Bitstream option). Otherwise, DOUT is high-impedance.
  5. CSO_B is only used in a parallel configuration daisy-chain for outputting a chip-enable signal to a downstream device. Otherwise, CSO_B is high-impedance.
  6. RS0 and RS1 are only driven in BPI mode when a MultiBoot event is initiated or when the Configuration Fallback option is enabled and a Fallback event occurs. Otherwise, RS0 and RS1 are high-impedance. RS[1:0] pins are not recommended to be used in User mode when they are used for configuration.
  7. Dashes indicate that the pin is not used in the configuration mode and is high-impedance and ignored during configuration.
Table 2. Configuration Pins - Parallel Modes
Pin Name Bank Master BPI Master SelectMAP Slave SelectMAP
x8 x16 x8 x16 x8 x16 x32
POR_OVERRIDE N/A POR_OVERRIDE POR_OVERRIDE POR_OVERRIDE POR_OVERRIDE POR_OVERRIDE POR_OVERRIDE POR_OVERRIDE
VBATT N/A VBATT VBATT VBATT VBATT VBATT VBATT VBATT
CFGBVS 1 0 CFGBVS CFGBVS CFGBVS CFGBVS CFGBVS CFGBVS CFGBVS
M[2:0] 0 M[2:0]=010 M[2:0]=010 M[2:0]=100 M[2:0]=100 M[2:0]=110 M[2:0]=110 M[2:0]=110
TCK 0 TCK TCK TCK TCK TCK TCK TCK
TMS 0 TMS TMS TMS TMS TMS TMS TMS
TDI 0 TDI TDI TDI TDI TDI TDI TDI
TDO 0 TDO TDO TDO TDO TDO TDO TDO
PROGRAM_B 0 PROGRAM_B PROGRAM_B PROGRAM_B PROGRAM_B PROGRAM_B PROGRAM_B PROGRAM_B
INIT_B 0 INIT_B INIT_B INIT_B INIT_B INIT_B INIT_B INIT_B
DONE 0 DONE DONE DONE DONE DONE DONE DONE
CCLK 0 CCLK CCLK CCLK CCLK CCLK CCLK CCLK
PUDC_B 2 0 PUDC_B 2 PUDC_B 2 PUDC_B 2 PUDC_B 2 PUDC_B 2 PUDC_B 2 PUDC_B 2
RDWR_FCS_B 0 FCS_B FCS_B RDWR_B RDWR_B RDWR_B RDWR_B RDWR_B
D00_MOSI 0 D00 D00 D00 D00 D00 D00 D00
D01_DIN 0 D01 D01 D01 D01 D01 D01 D01
D02 0 D02 D02 D02 D02 D02 D02 D02
D03 0 D03 D03 D03 D03 D03 D03 D03
D[07:04] 65 D[07:04] D[07:04] D[07:04] D[07:04] D[07:04] D[07:04] D[07:04]
D[15:08] 65 - D[15:08] - D[15:08] - D[15:08] D[15:08]
A[15:00]_D[31:16] 65 A[15:00] A[15:00] - - - - D[31:16]
EMCCLK 3 65 EMCCLK 3 EMCCLK 3 EMCCLK 3 EMCCLK 3 - - -
CSI_ADV_B 65 ADV_B ADV_B CSI_B CSI_B CSI_B CSI_B CSI_B
DOUT_CSO_B 4 5 65 CSO_B 5 CSO_B 5 CSO_B 5 CSO_B 5 CSO_B 5 CSO_B 5 CSO_B 5
A[28:16] 65 A[28:16] A[28:16] - - - - -
FOE_B 65 FOE_B FOE_B - - - - -
FWE_FCS2_B 65 FWE_B FWE_B - - - - -
RS0, RS1 6 65 RS0, RS1 6 RS0, RS1 6 - - - - -
  1. CFGBVS is available in UltraScale FPGAs only.
  2. PUDC_B has special functionality during configuration but is independent of all configuration interfaces, that is, PUDC_B does not need to be voltage compatible with other pins in a configuration interface.
  3. EMCCLK is only used when the external master CCLK enable option enables EMCCLK as an input for clocking the master configuration modes.
  4. DOUT is only used in a serial configuration daisy-chain for outputting data to the downstream FPGA (or for the Debug Bitstream option). Otherwise, DOUT is high-impedance.
  5. CSO_B is only used in a parallel configuration daisy-chain for outputting a chip-enable signal to a downstream device. Otherwise, CSO_B is high-impedance.
  6. RS0 and RS1 are only driven in BPI mode when a MultiBoot event is initiated or when the Configuration Fallback option is enabled and a Fallback event occurs. Otherwise, RS0 and RS1 are high-impedance. RS[1:0] pins are not recommended to be used in User mode when they are used for configuration.
  7. Dashes indicate that the pin is not used in the configuration mode and is high-impedance and ignored during configuration.