Configuration Pin Definitions - Configuration Pin Definitions - UG570

Reduces T_POR time (from power up to INIT_B rise) as specified in data sheet. Connect directly to V_CCINT for a shorter T_POR time if required and if supported by the power-up timing of the configuration data source. Connect to GND for standard longer POR delay.

Serial, SPI, SelectMAP, BPI, JTAG

(with BBRAM encryption)

Active-Low reset to configuration logic. When PROGRAM_B is pulsed Low, the FPGA configuration is cleared and a new configuration sequence is initiated. Configuration reset is initiated upon the falling edge, and configuration (that is, programming) sequence begins upon the following rising edge. PROGRAM_B can externally be held Low during power-up to stall the power-on configuration sequence at the end of the initialization process. If PROGRAM_B is held Low, JTAG operations can be restricted. Dedicated pins remain disabled while PROGRAM_B is held Low.

Connect PROGRAM_B to an external ≤ 4.7 kΩ pull-up resistor to V_{CCO_0} to ensure a stable High input. Recommended push-button to GND to enable manual configuration reset.

Active-Low FPGA initialization pin or configuration error signal. The FPGA drives this pin Low when the FPGA is in a configuration reset state, when the FPGA is initializing (clearing) its configuration memory, or when the FPGA has detected a configuration error. Note that INIT_B does not drive Low when V_CCINT is powered down. In UltraScale+ devices the INIT_B pin might be seen as High (because of external resistors on board for INIT_B) for approximately 40 ms after power ON. The initial High time depends on the POR_OVERRIDE setting. With POR_OVERRIDE Low, the High time is approx. 40 ms. With POR_OVERRIDE High, the High time is approx. 9 ms.)

Upon completing the FPGA initialization process, INIT_B is released to high-impedance at which time an external resistor is expected to pull INIT_B High. INIT_B can externally be held Low during power-up to stall the power-on configuration sequence at the end of the initialization process. When a High is detected at the INIT_B input after the initialization process, the FPGA proceeds with the remainder of the configuration sequence dictated by the M[2:0] pin settings. After configuration, INIT_B can optionally be leveraged to indicate when the FPGA has detected a configuration error.

Connect INIT_B to a 4.7 kΩ pull-up resistor to V_{CCO_0} to ensure clean Low-to-High transitions.

A High signal on the DONE pin indicates completion of the configuration sequence. By default, the DONE output is open-drain.

Note: DONE has a default internal pull-up resistor of approximately 10 kΩ. External 4.7 kΩ resistor circuits are not required but are recommended. For multiple SLR devices the DONE pull-up resistor cannot be stronger than 4.7 kΩ.

In UltraScale+ devices the DONE pin might be seen as High (because of external resistors on board for DONE) for approximately 40 ms after power ON. (The initial High time depends on the POR_OVERRIDE setting. With POR_OVERRIDE Low, the High time is approx. 40 ms. With POR_OVERRIDE High, the High time is approx. 9 ms.)

Supported in Kintex UltraScale and Virtex UltraScale FPGAs only. Determines the I/O voltage operating range and voltage tolerance for the dedicated configuration bank 0, and during configuration for the configuration pins in bank 65, when those banks are HR I/O banks. Connect CFGBVS High or Low per the bank voltage requirements. If the V_{CCO_0} supply for bank 0 is supplied with 2.5V or 3.3V, then this pin must be tied High (connected to V_{CCO_0} ). Tie CFGBVS to Low (connect to GND) only if the V_{CCO_0} for bank 0 is 1.5V or 1.8V. When bank 65 is used for configuration, it should have the same voltage as bank 0. See Configuration Banks Voltage Select (Kintex UltraScale and Virtex UltraScale FPGAs).

Multi-

function

Multi-

function

Chip Select Input (bar) or

Address Valid (bar)

BPI

(synchronous)

Multi-

function

Data Output or

Chip Select Output (bar)

65 D

[03:00] are in Bank 0

Multi-

function

A subset or all of the D[31:00] pins are the data bus interface for the serial, SPI, SelectMAP, or BPI modes. By default, data from the data bus is captured on the rising edge of CCLK. The remaining data pins are unused, ignored, and high impedance during configuration, and D[31:04] can be used as I/O after configuration.

The data bus signals are inputs when reading the configuration data from the flash. Data bus signals can be outputs during a write to a parallel flash Read Configuration register or during SelectMAP readback. For serial and SPI modes, also see the D00-D03 rows in this table.

Configuration begins with the D00_MOSI and D01 pins of the data bus used for standard SPI (x1) serial data output and data input. Bitstream options can switch the flash read mode to dual output (x2), quad output (x4), or dual quad (x8) modes.

• For SPI x1/x2/x4/x8: Connect D00_MOSI to the flash serial data input (DQ0/D/SI/IO0) pin.
• For SPI x1/x2/x4/x8: Connect D01_DIN to the flash serial data output (DQ1/Q/SO/IO1) pin.
• For SPI x4/x8: Connect D02 to the flash quad data bit 2 output (DQ2/W#/WP#/IO2) pin and connect to an external 4.7 kΩ pull-up resistor to V_{CCO_0} .
• For SPI x4/x8: Connect D03 to the flash quad data bit 3 output (DQ3/HOLD#/IO3) pin and connect to an external 4.7 kΩ pull-up resistor to V_{CCO_0} .
• For SPI x8: Connect D[07:04] to the second flash in the same way as D[03:00] are connected to the first flash.

The FPGA monitors the D[07:00] for an auto-bus-width-detect pattern that determines whether only D[07:00] (x8 bus width) are used or a wider (x16 or x32) data bus width is used. Connect used data bus pins to the corresponding data pins on the data source.

The data bus signals are inputs when reading the configuration data from the flash, and outputs during readback.

A[15:00]_

D[31:16]

Multi-

function

Serial,

SPI, BPI, SelectMAPx8/x16, JTAG

Multi-

function

Multi-

function

Multi-

function

Flash Write-Enable (bar)

or

Flash Chip Select 2 (bar)

Serial,

SPI x1/x2/x4, SelectMAP, JTAG

Multi-

function