Configuration Options Register 1 (01110) - Configuration Options Register 1 (01110) - UG570

UltraScale Architecture Configuration User Guide (UG570)

Document ID
UG570
Release Date
2025-03-04
Revision
1.20.1 English

Configuration Options Register 1 (COR1) is used to set certain configuration options for the device. The name of each bit position in the COR1 is given in the following table and described in the subsequent table.

Table 1. Configuration Options Register 1
Description Reserved RBCRC_ACTION Reserved RBCRC_NO_PIN RBCRC_EN Reserved BPI_1ST_READ_CYCLE BPI_PAGE_SIZE
Bit Index 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 2. Configuration Options Register 1 Description
Name Bit Index Description
Reserved [31:18] Reserved
RBCRC_ACTION [17:15]

Controls readback action:

000: Continue

Others: Reserved (use SEM IP for correction applications)

Reserved [14:10] Reserved
RBCRC_NO_PIN 9

Controls INIT_B as a readback CRC error status output pin:

0: Enables INIT_B as a readback CRC error status output pin (default)

1: Disables INIT_B as a readback CRC error status output pin

RBCRC_EN 8

Controls continuous readback CRC enable:

0: Disables continuous readback CRC (default)

1: Enables continuous readback CRC

Reserved [7:4] Reserved
BPI_1ST_READ_CYCLE [3:2]

First byte read timing:

00: 1 CCLK (default)

01: 2 CCLKs

10: 3 CCLKs

11: 4 CCLKs

Bitstream property: BITSTREAM.CONFIG.BPI_1ST_READ_CYCLE

BPI_PAGE_SIZE [1:0]

Flash memory page size:

00: 1 byte/word (default)

01: 4 bytes/words

10: 8 bytes/words

11: Reserved

Bitstream property: BITSTREAM.CONFIG.BPI_PAGE_SIZE