Configuration Options Register 0 (01001) - Configuration Options Register 0 (01001)

Configuration Options Register 0 (01001) - Configuration Options Register 0 (01001) - UG570

UltraScale Architecture Configuration User Guide (UG570)

Document ID

UG570

Release Date

2025-03-04

Revision

1.20.1 English

The configuration options register 0 (COR0) is used to set certain configuration options for the device. The name of each bit position in the COR0 is given in the following table and described in the subsequent table.

Table 1. Configuration Options Register 0
Description	Reserved					ECLK_EN	Reserved	DRIVE_DONE	Reserved	OSCFSEL						Reserved		DONE_CYCLE			MATCH_CYCLE			LOCK_CYCLE			GTS_CYCLE			GWE_CYCLE
Bit Index	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Value	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	0	1	1	0	0

Table 2. Configuration Options Register 0 Description
Name	Bit Index	Description
ECLK_EN	26	External master configuration clock (EMCCLK) enable. Bitstream property: BITSTREAM.CONFIG.EXTMASTERCCLK_EN.
DRIVE_DONE	24	0 : DONE pin is open drain `1`: DONE is actively driven High (not recommended)
OSCFSEL	[22:17]	Select CCLK frequency in master modes (3 MHz – 148 MHz for UltraScale FPGAs, and 2.7 MHz - 170 MHz for UltraScale+ FPGAs). Bitstream property: BITSTREAM.CONFIG.CONFIGRATE.
DONE_CYCLE	[14:12]	Start-up cycle to release the DONE pin: `000`: Start-up phase 1 `001`: Start-up phase 2 `010`: Start-up phase 3 `011`: Start-up phase 4 `100`: Start-up phase 5 `101`: Start-up phase 6 Bitstream property: BITSTREAM.STARTUP.DONE_CYCLE.
MATCH_CYCLE	[11:9]	Start-up cycle to stall in until DCI matches: `000`: Start-up phase 0 `001`: Start-up phase 1 `010`: Start-up phase 2 `011`: Start-up phase 3 `100`: Start-up phase 4 `101`: Start-up phase 5 `110`: Start-up phase 6 `111`: No wait Bitstream property: BITSTREAM.STARTUP.MATCH_CYCLE.
LOCK_CYCLE	[8:6]	Start-up cycle to stall in until MMCMs lock: `000`: Start-up phase 0 `001`: Start-up phase 1 `010`: Start-up phase 2 `011`: Start-up phase 3 `100`: Start-up phase 4 `101`: Start-up phase 5 `110`: Start-up phase 6 `111`: No wait Bitstream property: BITSTREAM.STARTUP.LCK_CYCLE.
GTS_CYCLE	[5:3]	Start-up cycle to deassert the Global 3-State (GTS) signal: `000`: Start-up phase 1 `001`: Start-up phase 2 `010`: Start-up phase 3 `011`: Start-up phase 4 `100`: Start-up phase 5 `101`: Start-up phase 6 `110`: GTS tracks DONE pin. Bitstream property: GTS_CYCLE:DONE.
GWE_CYCLE	[2:0]	Start-up phase to deassert the Global Write Enable (GWE) signal: `000`: Start-up phase 1 `001`: Start-up phase 2 `010`: Start-up phase 3 `011`: Start-up phase 4 `100`: Start-up phase 5 `101`: Start-up phase 6 `110`: GWE tracks DONE pin. Bitstream property: GWE_CYCLE:DONE