Configuration Memory Read Procedure (JTAG) - Configuration Memory Read Procedure (JTAG) - UG570

The process for reading configuration memory from the FDRO register through the JTAG interface is similar to the process for reading from other registers. However, additional steps are needed to accommodate frame logic. Configuration data coming from the FDRO register pass through the frame buffer, therefore, the first frame of readback data is dummy data and should be discarded (refer to the FDRI and FDRO register description). The JTAG readback flow is recommended for most users.

1. Reset the TAP controller.
2. Shift the CFG_IN instruction into the JTAG Instruction register. The LSB of the CFG_IN instruction is shifted first; the MSB is shifted while moving the TAP controller out of the SHIFT-IR state.
3. Shift packet write commands into the CFG_IN register through the Shift-DR state:
   1. Write a dummy word to the device.
   2. Write the synchronization word to the device.
   3. Write at least one NOOP instruction to the device.
   4. Write the RCRC command to the device.
   5. Write two dummy words to flush the packet buffer.
4. Shift the JSHUTDOWN instruction into the JTAG Instruction register.
5. Move into the RTI state; remain there for 12 TCK cycles to complete the shutdown sequence. The DONE pin goes Low during the shutdown sequence.
6. Shift the CFG_IN instruction into the JTAG Instruction register.
7. Move to the Shift-DR state and shift packet write commands into the CFG_IN register:
   1. Write a dummy word to the device.
   2. Write the synchronization word to the device.
   3. Write at least one NOOP instruction to the device.
   4. Write the write CMD register header.
   5. Write the RCFG command to the device.
   6. Write the write FAR register header.
   7. Write the starting frame address to the FAR register (typically 0x0000000 ).
   8. Write the read FDRO register Type 1 packet header to the device.
   9. Write a Type 2 packet header to indicate the number of words to read from the device.
   10. Write two dummy words to the device to flush the packet buffer.

       The MSB of all configuration packets sent through the CFG_IN register must be sent first. The LSB is shifted while moving the TAP controller out of the SHIFT-DR state.

8. Shift the CFG_OUT instruction into the JTAG Instruction register through the Shift-DR state. The LSB of the CFG_OUT instruction is shifted first; the MSB is shifted while moving the TAP controller out of the SHIFT-IR state.
9. Shift frame data from the FDRO register through the Shift-DR state.
10. Reset the TAP controller.

The following table shows the shutdown readback command sequence.