FPGA configuration memory is arranged in frames that are tiled about the device. These frames are the smallest addressable segments of the FPGA configuration memory space, and all operations must therefore act upon whole configuration frames. All frames have a fixed, identical length. Depending on bitstream options, additional overhead exists in the configuration bitstream. The exact bitstream length is available in the rawbits file (RBT) created by using the raw_bitfile option when using the bitstream generator or by selecting Create ASCII Configuration File in the Generate Programming File options popup in the Vivado tools. Bitstream length (words) is roughly equal to the configuration array size (words) plus configuration overhead (words). Bitstream length (bits) is roughly equal to the bitstream length in words times 32. See Table 1.