Configuration Interfaces - Configuration Interfaces - UG570

UltraScale Architecture Configuration User Guide (UG570)
Document ID
UG570
Release Date
2025-03-04
Revision
1.20.1 English

AMD UltraScale FPGAs have seven configuration interfaces, and UltraScale+ FPGAs have five configuration interfaces. Each configuration interface corresponds to one or more configuration modes and bus width, shown in the following table. For detailed interface timing information, see the respective data sheet Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics (DS892)) or Virtex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics (DS893).

Table 1. Configuration Modes
Configuration Mode M[2:0] Bus Width CCLK Direction
Master serial 1 000 x1 Output
Master SPI 001 x1, x2, x4, x8 Output
Master BPI 010 x8, x16 Output
Master SelectMAP 1 100 x8, x16 Output
JTAG only 2 101 x1 N/A
Slave SelectMAP 110 x8, x16, x32 Input
Slave Serial 3 111 x1 Input
  1. Not recommended in UltraScale FPGAs, and not supported in UltraScale+ FPGAs. See Differences Between UltraScale FPGA Families.
  2. JTAG mode is always available independent of the Mode pin settings. Setting the Mode pins to JTAG-only is not recommended for devices based on SSI technology due to restrictions on ICAP access.
  3. Slave serial is the default setting due to internal pull-up resistors on the Mode pins.