Configuration Banks Voltage Select (Kintex UltraScale and Virtex UltraScale FPGAs) - Configuration Banks Voltage Select (Kintex UltraScale and Virtex UltraScale FPGAs) - UG570

In the Kintex UltraScale and Virtex UltraScale FPGAs, the configuration banks voltage select (CFGBVS) pin must be set to High or Low to determine the I/O voltage support for the pins in bank 0, and for the multi-function pins in bank 65 when they are used during configuration. The CFGBVS is a logic input pin referenced between V_{CCO_0} and GND. When the CFGBVS pin is connected to the V_{CCO_0} supply of 3.3V or 2.5V, the configuration I/O support operation at 3.3V or 2.5V. When the CFGBVS pin is connected to GND, the configuration I/O support operation at 1.8V or 1.5V. There is no CFGBVS pin in the Artix UltraScale+, Kintex UltraScale+, and Virtex UltraScale+ FPGAs because their configuration I/O only support operation at 1.8V or 1.5V. The pin location is labeled RSVDGND and it must be connected to GND.

Configuration is not supported below the minimum recommended operating voltage for 1.5V as specified in the data sheet. The CFGBVS pin setting determines the I/O voltage support for bank 0 at all times, before, during, and after configuration. CFGBVS similarly controls the voltage tolerance on bank 65, but only during configuration.

The UltraScale FPGAs have two I/O bank types for configuration: high-range (HR) I/O banks support 3.3V and lower I/O standards, and high-performance (HP) banks support I/O standards of 1.8V or lower. The dedicated configuration and JTAG I/O are located in bank 0, which is a high-range bank type on all Kintex UltraScale and Virtex UltraScale devices, and a high-performance bank in Artix UltraScale+, Kintex UltraScale+, and Virtex UltraScale+ devices. Several of the configuration modes also rely on pins in bank 65. Bank 65 is an HR bank in most Kintex UltraScale FPGAs, an HP bank in the KU095 and Virtex UltraScale FPGAs, and an HP bank in all Artix UltraScale+, Kintex UltraScale+, and Virtex UltraScale+ FPGAs.

The following table shows the CFGBVS pin connection options and the corresponding set of valid V_{CCO_0} supply and I/O voltages.

The interface pins associated with the configuration mode can span bank 0 and bank 65, primarily when using 8-bit or wider data interfaces. When both banks are used for a configuration interface, the V_CCO pins for both banks must receive the same voltage to ensure a consistent I/O voltage interface and timing for all of the configuration interface pins. Using the same voltage for banks 0 and 65 is recommended because it allows the option of using an 8-bit or wider configuration mode, and avoids the I/O transition described under I/O Transition at the End of Startup.

Use these steps to determine the proper CFGBVS pin setting:

1. Determine the configuration mode(s) for the FPGA.
   Note: The JTAG interface is always supported in bank 0 at the V_{CCO_0} voltage level regardless of the configuration mode.
2. For each configuration mode to be used for the FPGA, determine the set of pins used for the configuration mode and the bank locations (see Table 1 and Table 2).
3. For each set of configuration pins, determine the common required I/O voltage support for the required configuration bank(s).
4. Determine the target FPGA family. The Virtex UltraScale and Kintex KU095 FPGAs only support 1.8V/1.5V configuration on bank 65.
5. Set the CFGBVS pin to support the required configuration I/O voltage. See the following tables for the appropriate CFGBVS pin setting.