Configuration Abort Sequence Description - Configuration Abort Sequence Description - UG570

An ABORT is signaled during configuration as follows:

1. The configuration sequence begins normally.
2. Pull the RDWR_B pin High synchronous to CCLK while the device is selected (CSI_B asserted Low).
3. The FPGA drives the status word onto the data pins if RDWR_B remains set for read control (logic High).
4. The ABORT lasts for four clock cycles, and Status is updated. See the following figure.