Command Register (00100) - Command Register (00100)

Command Register (00100) - Command Register (00100) - UG570

UltraScale Architecture Configuration User Guide (UG570)

Document ID

UG570

Release Date

2025-03-04

Revision

1.20.1 English

The command register (CMD) is used to instruct the configuration control logic to strobe global signals and perform other configuration functions. The command present in the CMD register is executed each time the FAR register is loaded with a new value. The following table lists the command register commands and codes.

Table 1. Command Register Codes
Command	Code	Description
NULL	`00000`	Null command, no action.
WCFG	`00001`	Writes configuration data: used prior to writing configuration data to the FDRI.
MFW	`00010`	Multiple frame write: used to perform a write of a single frame data to multiple frame addresses.
DGHIGH/ LFRM	`00011`	Last frame: Deasserts the GHIGH_B signal, activating all interconnects. The GHIGH_B signal is asserted with the AGHIGH command.
RCFG	`00100`	Reads configuration data: used prior to reading configuration data from the FDRO.
START	`00101`	Begins the start-up sequence: start-up sequence begins after a successful CRC check and a DESYNC command are performed.
URAM	`00110`	Triggers clearing the URAM.
RCRC	`00111`	Resets CRC: Resets the CRC register.
AGHIGH	`01000`	Asserts the GHIGH_B signal: places all interconnect in a High-Z state to prevent contention when writing new configuration data. This command is only used in shutdown reconfiguration. Interconnect is reactivated with the LFRM command.
SWITCH	`01001`	Switches the CCLK frequency: updates the frequency of the master CCLK based on the ECLK_EN and OSCFSEL bits in the COR0 register.
GRESTORE	`01010`	Pulses the GRESTORE signal: sets/resets (depending on user configuration) CLB flip-flops.
SHUTDOWN	`01011`	Begin shutdown sequence: Initiates the shutdown sequence, disabling the device when finished. Shutdown activates on the next successful CRC check or RCRC instruction (typically an RCRC instruction).
DESYNC	`01101`	Resets the DALIGN signal: Used at the end of configuration to desynchronize the device. After desynchronization, all values on the configuration data pins are ignored.
IPROG	`01111`	Internal PROG for triggering a warm boot.
CRCC	`10000`	When readback CRC is selected, the configuration logic recalculates the first readback CRC value after reconfiguration. Toggling GHIGH has the same effect. This command can be used when GHIGH is not toggled during the reconfiguration case.
LTIMER	`10001`	Reload watchdog timer.
BSPI_READ	`10010`	For BPI and SPI configuration modes, this command re-initiates the bitstream read. In Master SPI configuration mode: When the FPGA default SPI bus width (1-bit) or default address command (24-bit) is changed, a BSPI_READ command is issued to read the bitstream again starting at 0x0. In Master BPI configuration mode: When the BPI synchronous read option is used a BSPI_READ command gets issued to read the bitstream again starting at 0x0 after it executes the switch from asynchronous read to synchronous read. If BSPI_READ was previously executed or a fallback occurs, the BSPI_READ command is skipped.
FALL_EDGE	`10011`	Switch to negative edge clocking (configuration data capture on falling edge).