Clocking Serial Configuration Data - Clocking Serial Configuration Data - UG570

The following figure shows how configuration data is clocked into FPGAs in slave serial and master serial modes.

Notes relevant to the previous figure:

1. Bit 0 represents the MSB of the first byte. For example, if the first byte is 0xAA. (1010_1010), bit 0 = 1, bit 1 = 0, bit 2 = 1, etc.
2. For master serial configuration mode, CCLK is driven only after INIT_B goes High to shortly after DONE goes High. Otherwise CCLK is in a high-impedance state.
3. CCLK can be free-running in slave serial mode.