Clear Configuration Memory (Step 2, Initialization) - Clear Configuration Memory (Step 2, Initialization) - UG570

Configuration memory (see the following figure) is cleared sequentially each time the device is powered up, after the PROGRAM_B pin is pulsed Low, after the JTAG JPROGRAM instruction or the IPROG command are used, or during a fallback retry configuration sequence. Block RAM and flip-flops can be initialized during configuration.

During this time, I/Os are drivers are disabled, except for the configuration and JTAG pins, through the use of the global three-state (GTS). User I/O pins are High-Z or pulled up depending on whether PUDC_B is High or Low, respectively. Both the dedicated configuration bank 0 and the multi-function bank 65 are enabled during configuration, independent of the mode pins. In devices based on SSI technology, banks 60 and 70 are also enabled during configuration, although they do not have configuration functions.

INIT_B is internally driven Low during initialization, then released after TPOR (see the following figure) for the power-up case, and T_PL for MultiBoot and fallback cases. If the INIT_B pin is held Low externally, the device waits in the initialization process until the pin is released, and the TPOR or T_PL delay is met.

The minimum Low pulse time for PROGRAM_B is defined by the TPROGRAM timing parameter.