As the configuration data frames are loaded, the
device calculates a cyclic redundancy check (CRC) value from the configuration data packets.
After the configuration data frames are loaded, the configuration bitstream can issue a check
CRC instruction to the device, followed by an expected CRC value. If the CRC value calculated
by the device does not match the expected CRC value in the bitstream, the device pulls
INIT_B Low and aborts configuration. The CRC check is included in the
configuration bitstream by default, although you can disable it using BITSTREAM.GENERAL.CRC
DISABLE, and you can disable the INIT_B error signal with
BITSTREAM.CONFIG.INITSIGNALSERROR DISABLE. The CRC check and INIT_B error
signal are recommended. If the CRC check is disabled, there is a risk of loading incorrect
configuration data frames, causing incorrect design behavior or damage to the device.
For encrypted bitstreams (when the BITSTREAM.ENCRYPTION.ENCRYPT property is Yes), the CRC check is disabled and instead the AES-GCM authenticates the encrypted bitstream data. Errors in the bitstream data are reported in the status register as a security error.
If a CRC error occurs during configuration from a
mode where the FPGA is the configuration master, the device can attempt to do a fallback
reconfiguration. In BPI and SPI modes, if fallback reconfiguration fails again, the BPI/SPI
interface can only be resynchronized by pulsing the PROGRAM_B pin and
restarting the configuration process from the beginning. The JTAG interface is still
responsive and the device is still active, only the BPI/SPI interface is inoperable. In
SelectMAP modes, either the PROGRAM_B pin can be pulsed Low or an ABORT
sequence can be initiated (see SelectMAP Configuration Modes).
AMD devices use a
32-bit CRC check. The CRC check is designed to catch errors in transmitting the configuration
bitstream. There is a scenario where errors in transmitting the configuration bitstream can be
missed by the CRC check: certain clocking errors, such as double-clocking, can cause loss of
synchronization between the 32-bit bitstream packets and the configuration logic. After
synchronization is lost, any subsequent commands are not understood, including the command to
check the CRC, and the device does not complete configuration. In this situation,
configuration fails with DONE Low and INIT_B High because the CRC was ignored. In BPI Mode asynchronous read, the
address counter eventually overflows or underflows to cause wraparound, which triggers
fallback reconfiguration. BPI synchronous read mode does not support the wraparound error
condition.