All activity on the SelectMAP data bus is synchronous to
CCLK. When RDWR_B is set for write
control (RDWR_B = 0, Configuration), the
FPGA samples the SelectMAP data pins on rising CCLK edges.
When RDWR_B is set for read control
(RDWR_B = 1, Readback), the FPGA
updates the SelectMAP data pins on rising CCLK edges.
In slave SelectMAP mode, configuration can be paused by
stopping CCLK (see Non-Continuous SelectMAP Data Loading).