Bus Width Auto Detection - Bus Width Auto Detection - UG570

For parallel configuration modes, the bus width is auto-detected by the configuration logic. A bus width detection pattern is put in the front of every bitstream (BIT or RBT). Because it appears before the Sync word, serial configuration modes ignore it (master serial, slave serial, JTAG, or SPI mode). The configuration logic only checks the low eight bits of the parallel bus. Depending on the byte sequence received, the configuration logic can automatically switch to the appropriate external bus width. The following table shows an example bitstream with an inserted bus width detection pattern. When observing the pattern on the FPGA data pins, the bits are bit swapped, as described in Parallel Bus Bit Order.

The bitstream data in the following table shows the 32-bit configuration word for an unswapped bitstream. For swapped and unswapped formats, see Configuration Data File Formats.

For the x8 bus, the configuration bus width detection logic first finds 0xBB on the D[0:7] pins, followed by 0x11. For the x16 bus, the configuration bus width detection logic first finds 0xBB on D[0:7] followed by 0x22. For the x32 bus, the configuration bus width detection logic first finds 0xBB, on D[0:7], followed by 0x44. See the following table.

If the immediate byte after 0xBB is not 0x11, 0x22, or 0x44, the bus width state machine is reset to search for the next 0xBB until a valid sequence is found. Then, it switches to the appropriate external bus width and starts looking for the Sync word. When the bus width is detected, the SelectMAP interface is locked to that bus width until a power cycle, PROGRAM_B pulse, JPROGRAM reset, or IPROG reset is issued.