UltraScale architecture is fully compliant with the IEEE Standard 1149.1 Test Access Port and Boundary-Scan Architecture. The UltraScale FPGAs include all mandatory elements defined in the IEEE 1149.1 standard. These elements include the TAP, the TAP controller, the Instruction register, the Instruction decoder, the Boundary register, and the Bypass register. UltraScale FPGAs also support a 32-bit Device Identification register and a Configuration register. This section outlines the details of the JTAG architecture.