UltraScale architecture-based FPGAs include all registers required by IEEE Std 1149.1. In addition to the standard registers, the family contains optional registers for simplified testing and verification (see the following table).
| Register Name | Register Length | Description |
|---|---|---|
| Boundary Register | 3 bits per I/O | Controls and observes input, output, and output enable. |
| Instruction Register | 6 bits 1 | Holds the current instruction opcode and captures internal device status. Refer to Table 1. |
| Bypass Register | 1 bit | Bypasses the device. |
|
Device Identification Register |
32 bits | Captures the device ID. |
| JTAG Configuration Register | Varies | Allows access to the configuration bus when using the CFG_IN or CFG_OUT instructions. |
| USERCODE Register | 32 bits | Captures the user-programmable code. |
| User-Defined Registers (USER1, USER2, USER3, and USER4) | Design specific | Design specific. |
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