The test primary data register is the Boundary register. Boundary-scan operation is independent of individual IOB configurations. Each IOB, bonded or unbonded, starts as bidirectional with 3-state control. Later, it can be configured to be an input, output, or 3-state only. Therefore, three data register bits are provided per IOB. The following figure is a representation of the UltraScale FPGA boundary-scan architecture.
When conducting a data register (DR) operation,
the DR captures data in a parallel fashion during the CAPTURE-DR state. The data is then
shifted out and replaced by new data during the SHIFT-DR state. For each bit of the DR, an
update latch is used to hold the input data stable during the next SHIFT-DR state. The data is
then latched during the UPDATE-DR state when TCK is Low.
The update latch is opened each time the TAP
controller enters the UPDATE-DR state. Care is necessary when exercising an
EXTEST to ensure that the proper data has been latched before exercising
the command. This is typically accomplished by using the SAMPLE/PRELOAD
instruction.
Internal pull-up and pull-down resistors should be
considered when test vectors are being developed for testing opens and shorts. The
PUDC_B pin determines whether the IOB has a pull-up resistor.
Bit Sequence of Boundary-Scan Register
This section describes the order of
each non-TAP IOB. The input is first, the output second, and the 3-state IOB control third.
The 3-state IOB control is closest to the TDO. The input- only pins
contribute only the input bit to the boundary-scan I/O data register. The bit sequence of
the device is obtainable from the Boundary-Scan Description Language Files (BSDL files) for
the UltraScale FPGAs. (The BSDL files can be obtained from
the AMD download area and represent an unconfigured FPGA.) The bit
sequence always has the same bit order and the same number of bits and is independent of the
design.
For boundary-scan testing with a
configured FPGA, AMD offers the write_bsdl utility to
automatically modify the BSDL file for post-configuration interconnect testing. The
write_bsdl utility obtains the necessary FPGA design information from the
implemented design, and generates a BSDL file that reflects the post-configuration
boundary-scan architecture of the device.