The boot history status register (BOOTSTS)
can only be reset by POR, asserting PROGRAM_B, or issuing
a JPROGRAM instruction. At EOS or an error condition, status (_0) is
shifted to status (_1), and status (_0) is updated with the current status. The name of each
bit position in the BOOTSTS register is given in the following table and described in the
subsequent table.
| Description | Reserved | WRAP_ERROR_1 | CRC_ERROR_1 | ID_ERROR_1 | WATCHDOG_TIMEOUT_ERROR_1 | INTERNAL_PROG_1 | FALLBACK_1 | STATUS_VALID_1 | Reserved | WRAP_ERROR_0 | CRC_ERROR_0 | ID_ERROR_0 | WATCHDOG_TIMEOUT_ERROR_0 | INTERNAL_PROG_0 | FALLBACK_0 | STATUS_VALID_0 | ||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Bit Index | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | Bit Index | Description |
|---|---|---|
| WRAP_ERROR_1 | 14 | BPI address counter wraparound error, supported in asynchronous read mode. |
| CRC_ERROR_1 | 13 | CRC error. |
| ID_ERROR_1 | 12 | IDCODE error. |
| WATCHDOG_TIMEOUT_ERROR_1 | 11 | Watchdog time-out error. |
| INTERNAL_PROG_1 | 10 | Internal PROG triggered configuration. |
| FALLBACK_1 | 9 |
|
| STATUS_VALID_1 | 8 | Status 1 is valid. |
| WRAP_ERROR_0 | 6 | BPI address counter wraparound error, supported in asynchronous read mode |
| CRC_ERROR_0 | 5 | CRC error. |
| ID_ERROR_0 | 4 | IDCODE error. |
| WATCHDOG_TIMEOUT_ERROR_0 | 3 | Watchdog time-out error. |
| INTERNAL_PROG_0 | 2 | Internal PROG triggered configuration. |
| FALLBACK_0 | 1 |
|
| STATUS_VALID_0 | 0 | Status 0 is valid. |
|
||