The BSCANE2 primitive allows access between the internal FPGA logic and the JTAG boundary scan logic controller. This allows for communication between the internal running design and the dedicated JTAG test access port (TAP) pins of the FPGA. The BSCANE2 primitive must be instantiated to gain internal access to the JTAG pins. The BSCANE2 primitive is not needed for normal JTAG operations that use direct access from the JTAG pins to the TAP controller. The BSCANE2 is automatically added to a design when using the Vivado Logic Analyzer, or when using indirect flash programming in the Vivado Device Programmer.
The BSCANE2 primitive is identical to that found in the 7 series FPGAs. For more details on boundary scan and usage of the BSCANE2 primitive, see Boundary-Scan and JTAG Configuration.