BPI/SPI Configuration Options Register (11111) - BPI/SPI Configuration Options Register (11111) - UG570

UltraScale Architecture Configuration User Guide (UG570)
Document ID
UG570
Release Date
2025-03-04
Revision
1.20.1 English

The BPI/SPI configuration options register (BSPI) is used to store certain configuration options for the device set by the tools. The name of each bit position in the BSPI register is given in the following table and described in the subsequent table.

Table 1. BPI/SPI Configuration Options Register (BSPI)
Description Reserved BPI_SYNC_MODE BPI_SYNC_RCR Reserved SPI_32BIT_ADDR SPI_BUSWIDTH SPI_READ_OPCODE
Bit Index 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1
Table 2. BPI/SPI Configuration Options Register Description
Name Bit Index Description
BPI_SYNC_MODE 27

BPI configuration flash read mode:

0: Asynchronous Read (default)

(See Master BPI Asynchronous Read)

1: Synchronous Read

(See Master BPI Synchronous Read)
BPI_SYNC_RCR [26:12]

BPI configuration flash Read Configuration register.

Determined by property BITSTREAM.CONFIG.BPI_SYNC_MODE options Type1 or Type2. See UltraScale FPGA BPI Configuration and Flash Programming (XAPP1220) for more information.
SPI_32BIT_ADDR 10

SPI address width:

0: 24-bit address (default)

1: 32-bit address

(See Serial NOR Flash Densities over 128 Mb)
SPI_BUSWIDTH [9:8]

SPI bus width:

00: x1 (default)

01: x2

10: x4

11: x8 (dual quad)
SPI_READ_OPCODE [7:0] SPI flash read instruction. See Table 1 Table 1.