The master BPI mode asynchronous read is the simplest parallel NOR flash setup, and significantly slower configuration times than the other read options. For the asynchronous read calculation, the following parameters must be considered:
- External master configuration clock
frequency (
EMCCLKRate) or FPGA nominal masterCCLKfrequency (Configuration Rate) - External master configuration clock
frequency tolerance (
EMCCLKTolerance) or FPGA masterCCLKfrequency tolerance (FMCCKTOL) - FPGA
CCLKrising edge to address valid (TBPICCO) - Parallel NOR flash address to output valid (access) time (TACC)
- FPGA data setup time (TBPIDCC)
The following equation is the basic
calculation to determine the configuration clock rate or EMCCLK
rate:
Figure 1. Configuration Clock Rate
