The sequence for a successful master BPI
configuration with asynchronous read is shown in the following figure. After power-up, Mode
pins M[2:0] are sampled when the FPGA INIT_B output goes
High. If the master BPI configuration mode (M[2:0] = 010) is determined, the FPGA drives the flash control signals
FWE_B High, FOE_B Low, and FCS_B Low.
Although the CCLK output is not required to be connected to the parallel NOR
flash device for asynchronous read, the FPGA outputs an address after the rising edge of
CCLK, and the data is still sampled on the next rising edge of
CCLK. In the master BPI mode with asynchronous read, the address starts at
0 and increments by 1 until
the DONE pin is asserted. If the address reaches the maximum value (29'h1FFFFFFF) and configuration is not done (DONE
is not asserted), a wraparound error flag is raised in the Status register, and fallback
reconfiguration starts.
Figure 1. Master BPI Configuration Mode Asynchronous Read Waveform
