Asynchronous Page Read - Asynchronous Page Read - UG570

The master BPI mode asynchronous page read gives you faster configuration times than the basic asynchronous read but not as fast as using the synchronous read. With page reads the first word read from a multiword page takes a standard asynchronous read time, but the subsequent read of another word from the same page takes significantly less time. To determine the fastest configuration clock rate for your page read implementation the following timing parameters should be considered:

External master configuration clock frequency (EMCCLK Rate) or FPGA nominal master CCLK frequency (configuration Rate)

• External master configuration clock frequency tolerance (EMCCLK Tolerance) or FPGA master CCLK frequency tolerance (FMCCKTOL)
• FPGA CCLK rising edge to address valid (T_BPICCO)
• Parallel NOR flash address to output valid (access) time (T_ACC)
• Parallel NOR flash page address to output valid (access) time (T_APA)
• FPGA data setup time (T_BPIDCC)
• Parallel NOR flash, number of words per page (BPI page size)
• FPGA number of CCLK cycles for the first word read (BPI first read cycle)

The BPI Page Size option is set to the number of words in a page, as defined by the Parallel NOR flash data sheet. Because the Parallel NOR flash has different timing for the read of the first word of a page, and for the subsequent read of a word from the same page, two timing checks are required to ensure the validity of the Configuration Rate and First Read Cycle attribute values.

First, the Configuration Rate setting must be checked. The period for the worst-case (fastest) master CCLK frequency must be greater than the sum of the FPGA address valid time, flash page access time, and FPGA setup time, as shown in the following equation.

Second, the First Read Cycle must be checked. The First Read Cycle option specifies the number of FPGA CCLK cycles allocated for the reading of the first word of each page. The duration of the first read cycle is equivalent to the period of one CCLK cycle multiplied by the First Read Cycle option value. The worst-case allocated duration of the first read cycle must be greater than the sum of the FPGA address valid time, Parallel NOR flash read access time, and FPGA setup time, as shown in the following equation.