In addition to the basic asynchronous read support, the UltraScale FPGA supports parallel NOR asynchronous page reads. The asynchronous page reads enable faster configuration clock frequency than in the basic asynchronous mode. This read option is popular for parallel NOR flash devices that are not supported by the UltraScale FPGA synchronous read option.
In the asynchronous page read sequence, the
first word read from a multiword page takes a standard asynchronous read time and a
subsequent read of another word from the same page takes significantly less time. The
sequence of the page read operation is controlled by the FPGA bitstream. The generation
of a bitstream with page read support requires the setting of multiple bitstream
properties to take advantage of page read and maximize the CCLK
frequency. The page size bitstream property determines the number of words in each page.
Words other than the first word of each page are read in one master
CCLK cycle. The first read cycle bitstream property determines the
number of CCLK cycles that are allotted to reading the first word of
each page. Refer to File Generation for details on how
to set the page size and first read cycle.
After an FPGA reset, the default page size
is 1, the first access CCLK is 1, and the master CCLK
is running at the slowest default frequency. The configuration register (COR1) contains
parallel NOR flash page read control bits. After the COR1 register is programmed, the
BPI address timing switches at the page boundary as shown in the following figure. When
the command is received, the master CCLK switches to a user-desired
frequency, using it to load the rest of the configuration.