Applications - Applications - UG570

A typical user application requiring instantiation of the BSCANE2 is to create internal, private scan registers in the FPGA logic. These scan registers propagate through the FPGA logic, not through the boundary I/O as is true with standard JTAG boundary scan. Each instance of this primitive supports one JTAG USER instruction, with multiple instantiations differentiated with the JTAG_CHAIN attribute. To handle all four USER instructions (USER1 through USER4), instantiate four BSCANE2 primitives and set the JTAG_CHAIN attribute uniquely on each.

For 3D ICs based on SSI technology, the BSCANE2 can only be instantiated in the master SLR. The tools automatically place the element in the correct SLR. Only the JTAG port on the master SLR can be accessed by the BSCANE2 primitive. For more details on SSI technology, see UltraScale Architecture and Product Data Sheet: Overview (DS890).

The BSCANE2 primitive can also be used to control or monitor activity on the JTAG TAP port. A signal on the TDO input of the primitive passes through an output timing register, where the TDO input to the primitive is registered on the falling edge of TCK as it is passed to the external TDO output pin when a USER instruction is active. The associated primitive's SEL output goes High to indicate which USER1–USER4 instruction is active. The DRCK output provides access to the data register clock generated by the TAP controller.

The RESET, UPDATE, SHIFT, and CAPTURE pins represent the decoding of the corresponding state of the boundary scan internal state machine. The TDI port provides access from the external TDI pin of the JTAG TAP to shift data into an internal scan chain. The TCK and TMS pins are similarly monitored through the BSCANE2 primitive.

The BSCANE2 primitive can be used to disable the external JTAG port by instantiating it and setting the attribute .DISABLE_JTAG("TRUE"). This prevents re-configuration through JTAG, including with the Vivado Device Programmer, by breaking the JTAG chain. This method is preferred over the write_bitstream option Bitstream.general.disable_jtag:Yes (default is No). The primitive has priority; JTAG cannot be enabled by write_bitstream if it is disabled in the BSCANE2 attribute.

AMD UltraScale+ devices add special internal pin names for the timing of some of the BSCANE2 pins. For constraints on BSCANE2 timing paths, use the following internal pin names for listed BSCANE2 pins.

Example constraints for the special internal BSCANE2 timing pins:

• BSCANE2.TDO
  • A 20 MHz (50 ns period), 50% duty cycle TCK clock constraint on BSCANE2.INTERNAL_TCK clock source pin covers timing path from source register clocked by BSCANE2.TCK through BSCANE2.TDO to the falling-edge BSCANE2.INTERNAL_TDO register. Device TDO output timing is defined by data sheet T_TCKTDO.

create_clock -name TCK -period 50 -waveform {0 25} [get_pins */INTERNAL_TCK]

• BSCANE2.TDI
  • An input delay constraint for an external source with a falling-edge clock-to-output valid time of 15.0 ns, max through device TDI input pin through BSCANE2.INTERNAL_TDI pin through BSCANE2.TDI port to fabric register.

set_input_delay 15 -clock_fall -clock [get_clocks TCK] [get_pins BSCAN/INTERNAL_TDI]

• BSCANE2.TMS
  • An input delay constraint for an external source falling-edge clock-to-output valid time of 15.0 ns, maximum through device TMS input pin through BSCANE2.INTERNAL_TMS pin through BSCANE2.TMS port to fabric register.

set_input_delay 15 -clock_fall -clock [get_clocks TCK] [get_pins BSCAN/INTERNAL_TMS]