Accessing Configuration and Configuration Memory through the SelectMAP Interface - Accessing Configuration and Configuration Memory through the SelectMAP Interface - UG570

To read configuration registers and configuration memory through the SelectMAP interface, set the interface for write control to send commands to the FPGA, and then switch the interface to read control to read data from the device. Write and read control for the SelectMAP interface is determined by the RDWR_B input: the SelectMAP data pins are inputs when the interface is set for Write control (RDWR_B = 0); they are outputs when the interface is set for Read control (RDWR_B = 1). The CSI_B signal must be deasserted (CSI_B =1) before toggling the RDWR_B signal to avoid an abort (refer to SelectMAP ABORT for details).

The procedure for changing the SelectMAP interface between Write and Read Control is:

1. Deassert CSI_B.
2. Toggle RDWR_B.
   • RDWR_B = 0: Write control
   • RDWR_B = 1: Read control
3. Assert CSI_B.
4. CSI_B and RDWR_B are synchronous to CCLK.

5. Readback configuration register data is valid on the fourth rising clock edge after the CSI_B pin is asserted (CSI_B = 0) during readback. Readback configuration memory data is valid on the fifth rising clock edge after the CSI_B pin is asserted (CSI_B = 0) during readback (see the following figures).