JTAG access to the FPGA configuration logic is provided through the JTAG CFG_IN and CFG_OUT registers. The CFG_IN and CFG_OUT registers are not configuration registers, rather they are JTAG registers like bypass and boundary. Data shifted into the CFG_IN register go to the configuration packet processor, where they are processed in the same way commands from the SelectMAP interface are processed.
Readback commands are written to the configuration logic by going through the CFG_IN register; configuration memory is read through the CFG_OUT register. The JTAG state transitions for accessing the CFG_IN and CFG_OUT registers are described in thw following table.
| Step | Description | Set and Hold | Number of Clocks (TCK) | |
|---|---|---|---|---|
| TDI | TMS | |||
| 1 | Clock five 1 s on TMS to bring the device to the TLR state |
X
|
1
|
5 |
| 2 | Move into the RTI state |
X
|
0
|
1 |
| 3 | Move into the Select-IR state |
X
|
1
|
2 |
| 4 | Move into the Shift-IR State |
X
|
0
|
2 |
| 5 | Shift the first five bits of the CFG_IN or CFG_OUT instruction, LSB first |
00101 (CFG_IN) |
0
|
5 |
00100 (CFG_OUT) |
||||
| 6 | Shift the MSB of the CFG_IN or CFG_OUT instruction while exiting SHIFT-IR |
0
|
1
|
1 |
| 7 | Move into the SELECT-DR state |
X
|
1
|
2 |
| 8 | Move into the SHIFT-DR state |
X
|
0
|
2 |
| 9 | Shift data into the CFG_IN register or out of the CFG_OUT register while in SHIFT_DR, MSB first |
X
|
0
|
X |
| 10 | Shift the LSB while exiting SHIFT-DR |
X
|
1
|
1 |
| 11 | Reset the TAP by clocking five 1s on TMS |
X
|
1
|
5 |