A High-Speed Configuration Option - A High-Speed Configuration Option - UG570

Some applications require that the logic be operational within a short time. Certain FPGA configuration modes and methods are faster than others. The configuration time includes the initialization time plus the configuration time. Configuration time depends on the size of the device and speed of the configuration logic.

• At the same clock frequency, parallel configuration modes are inherently faster than the serial modes because they program 8, 16, or 32 bits at a time.
• Configuring a single FPGA is inherently faster than configuring multiple FPGAs in a daisy-chain. In a multi-FPGA design, where configuration speed is a concern, each FPGA should be configured separately.
• In master modes, the FPGA internally generates the CCLK configuration clock signal. The maximum supported CCLK frequency setting depends on the read specifications for the attached nonvolatile memory. A faster memory enables faster configuration. When using the internal oscillator source for CCLK, the output frequency can vary with process, voltage, or temperature.
• Using the external EMCCLK clock source option enables a precision external clock source for optimal configuration performance.

The general calculation used to estimate the configuration time is given in the following equation.

The UltraScale FPGA bitstream size can be found in Table 1. The maximum configuration clock frequency is dependent on the configuration mode and application implementation. Guidelines to calculate the maximum configuration clock frequency are provided in Master SPI Configuration Mode, and Master BPI Configuration Mode. If the configuration time from power-up is required then T_POR should be added to the configuration time.

The AMD Vivado™ tools provide the Tcl command calc_config_time which can be used to estimate configuration time. Use help calc_config_time for usage information.