UltraScale Architecture Configuration User Guide (UG570) - UG570

Document ID: UG570
Release Date: 2025-03-04
Revision: 1.20.1 English

Introduction
Introduction to the UltraScale Architecture
Overview
Differences Between UltraScale FPGA Families
Differences from Previous Generations
KU025 Differences
Differences in 3D ICs
Design Considerations
FPGA Configuration Data Source
Master Modes
Slave Modes
JTAG Connection
A Basic Configuration Solution
A Low-Cost Configuration Solution
A High-Speed Configuration Option
Protecting a Bitstream
Loading Multiple FPGAs
Device Resources and Configuration Bitstream Lengths
Recommended Design Flow and Configuration Factors
Design Tools
Design Properties for Configuration
Configuration Bitstream Settings
Bitstream File Format Settings
Pinout Planning
Configuration Interfaces
Configuration Pins
Configuration Pin Definitions
Configuration Banks Voltage Select (Kintex UltraScale and Virtex UltraScale FPGAs)
Setting Configuration Voltage Options in the Vivado Tools
Power-On Reset
POR_OVERRIDE
Power-On Sequence Precautions for Flash
External Master Configuration Clock (EMCCLK) Option
VBATT
Master SPI Configuration Mode
Introduction
Master SPI Interface
Master SPI Read Commands
Master SPI Quad (x4)
Master SPI Dual Quad (x8)
Serial NOR Flash Densities over 128 Mb
Multi-die Serial NOR Flash Devices
SPI Configuration Timing
Determining the Maximum Configuration Clock Frequency
Power-on Sequence Precautions
Additional Information
Serial Configuration Mode
Introduction
Slave Serial Configuration
Master Serial Configuration
Clocking Serial Configuration Data
Master BPI Configuration Mode
Introduction
Master BPI Interface
Master BPI Synchronous Read
Synchronous Read Sequence
EMCCLK Option
Master BPI Asynchronous Read
Asynchronous Read Sequence
Asynchronous Page Read Support
Configuration Time
Synchronous Read
Asynchronous Page Read
Asynchronous Read
Power-on Sequence Precautions
File Generation
Parallel NOR Flash Programming Options
SelectMAP Configuration Modes
Introduction
SelectMAP Configuration Interface
Single Device SelectMAP Configuration
SelectMAP Data Loading
CSI_B
RDWR_B
CCLK
Continuous SelectMAP Data Loading
Non-Continuous SelectMAP Data Loading
SelectMAP Data Ordering
SelectMAP ABORT
Configuration Abort Sequence Description
Readback Abort Sequence Description
ABORT Status Word
Resuming Configuration or Readback After an Abort
Boundary-Scan and JTAG Configuration
Introduction
Boundary-Scan Using IEEE Standard 1149.1
Test Access Port (TAP)
Boundary Scan Timing Parameters
Using Boundary Scan in AMD Devices
Boundary-Scan Design Considerations
JTAG Signal Routing
Providing Power
TAP Controller and Architecture
Boundary-Scan Architecture Registers
Boundary Register
Instruction Register
Bypass Register
Device Identification (IDCODE) Register
JTAG Configuration Register
USERCODE Register
USER1, USER2, USER3, and USER4 Registers
Using Boundary-Scan Configuration in UltraScale FPGAs
Single Device Configuration
Multiple Device Configuration
Design Entry
Introduction
BSCANE2
Primitive
Pin Descriptions
Attributes
Applications
DNA_PORTE2
Primitive
Pin Descriptions
Attributes
EFUSE_USR
Primitive
Pin Descriptions
Attributes
FRAME_ECCE3
FRAME_ECCE4
ICAPE3
Primitive
Pin Descriptions
Attributes
ICAPE3 Resources
MASTER_JTAG
Primitive
Pin Descriptions
STARTUPE3
Primitive
Pin Descriptions
Attributes
PROG_USR Attribute Description
STARTUPE3 Connections to Dedicated Pins
Timing Considerations for Flash Connections
USR_ACCESSE2
Primitive
Pin Descriptions
USR_ACCESSE2 Advanced Uses
Bitstream Security, eFUSEs, and Device DNA
Introduction
Readback Security
Bitstream Encryption and Authentication
AES System Overview
Rolling Keys
Creating an Encrypted Bitstream
Loading the Encryption Key
Loading Encrypted Bitstreams
Bitstream Encryption and Internal Configuration Access Port (ICAP)
VBATT
Bitstream Authentication
RSA Authentication
eFUSE
OTP eFUSE Registers
JTAG Instructions
Device Identifier (Device DNA)
Identifier Value and Operation
Extending Identifier Length
JTAG Access to Device Identifier
Configuration Details
Introduction
Configuration Data File Formats
Generating Configuration Memory Files
Files for Serial Daisy Chains
Files for SelectMAP Configuration
Bit Swapping
Parallel Bus Bit Order
Configuration Sequence
Setup (Steps 1-3)
Device Power-Up (Step 1)
Clear Configuration Memory (Step 2, Initialization)
Sample Mode Pins (Step 3)
Bitstream Loading (Steps 4-7)
Synchronization (Step 4)
Device ID Check (Step 5)
Load Configuration Data (Step 6)
CRC Check (Step 7)
Start-up Sequence (Step 8)
Clocking to End of Start-up
I/O Transition at the End of Startup
Configuration Bitstream
Bus Width Auto Detection
Sync Word
Configuration Memory Frames
Bitstream Composition
Configuration Packets
Packet Types
Configuration Registers
CRC Register (00000)
Frame Address Register (00001)
FDRI Register (00010)
FDRO Register (00011)
Command Register (00100)
Control Register 0 (00101)
MASK Register (00110)
Status Register (00111)
LOUT Register (01000)
Configuration Options Register 0 (01001)
MFWR Register (01010)
AES_IV Register (01011)
IDCODE Register (01100)
AXSS Register (01101)
Configuration Options Register 1 (01110)
Warm Boot Start Address Register (10000)
Watchdog Timer Register (10001)
Boot History Status Register (10110)
Control Register 1 (11000)
BPI/SPI Configuration Options Register (11111)
Readback Verification and CRC
Introduction
Persist Option
Readback Command Sequences
Accessing Configuration and Configuration Memory through the SelectMAP Interface
Configuration Register Read Procedure (SelectMAP)
Configuration Memory Read Procedure (SelectMAP)
Accessing Configuration Registers through the JTAG Interface
Configuration Register Read Procedure (JTAG)
Configuration Memory Read Procedure (JTAG)
Verifying Readback Data
Compare to Golden Readback File
Compare to Frame Data in Bitstream
SEU Detection and Correction
MultiBoot and Reconfiguration
Introduction
Fallback MultiBoot
Golden Image Initial System Setup
Golden Image and MultiBoot Image Design Requirements
Initial MultiBoot Image System Setup
Initial MultiBoot Design Considerations
BPI – Hardware RS Pin Design Considerations
MultiBoot Bitstream Spacing
Process Details for MultiBoot and Fallback
IPROG
WBSTAR Register
Watchdog Timer
FPGA End of Start-Up
User Monitor Mode
RS Pins
IPROG Reconfiguration
IPROG Using ICAP
IPROG Embedded in the Bitstream
Status Register for Fallback and IPROG Reconfiguration
Dynamic Reconfiguration of Functional Blocks
Configuring Multiple FPGAs
Introduction
Serial Configuration Modes
Serial Daisy Chain Configuration
Mixed Serial Daisy Chains
Guidelines and Design Considerations for Serial Daisy Chains
Ganged Serial Configuration
Parallel Configuration Modes
Multiple Device SelectMAP Configuration
Parallel Daisy Chain Configuration
Ganged SelectMAP Configuration
Ganged Asynchronous BPI Configuration
Configuration Debugging
Introduction
File Generation Review
Status Pin Handling
Mode Pins M[2:0]
PROGRAM_B Pin
CFGBVS Pin
PUDC_B
Status Register Use and JTAG Access
Verification and Readback
Configuration Sequence
Configuration Start-Up Considerations
Remote Update Considerations
Initial Debug Steps
Additional Resources and Legal Notices
Finding Additional Documentation
Support Resources
References
Revision History
Please Read: Important Legal Notices

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