Although it is not necessary to understand the various timing parameters to implement most designs using AMD software, a thorough timing model can assist advanced users in analyzing critical paths or planning speed-sensitive designs, especially in the larger and more complex 7 series FPGAs.
The user is recommended to use the models in this chapter with both the AMD Timing Analyzer and the section on switching characteristics in the respective 7 series FPGAs data sheet. All pin names, parameter names, and paths are consistent with the Timing Analyzer reports. Most of the CLB timing parameters found in the data sheet section on switching characteristics are described in this chapter.
Five categories of functions are described in this chapter:
CLB General Slice Timing Model and Parameters
CLB Slice Multiplexer Timing Model and Parameters
CLB Slice Carry-Chain Timing Model and Parameters
CLB Slice Distributed RAM Timing Model and Parameters (Available in SLICEM Only)
CLB Slice SRL Shift Register Timing Model and Parameters (Available in SLICEM Only)
For each category, three timing model sections are described:
- Functional element diagram– basic architectural schematic illustrating pins and connections.
- Timing parameters– definitions of the respective 7 series FPGAs data sheet timing parameters.
- Timing diagram– illustrates functional element timing parameters relative to each other.
The general form of a timing parameter name is T subscripted with a combination of the starting pin and the ending pin. For example, TCECK is the setup time from CE to the clock, and TCKCE is the hold time from the clock to CE being removed. In some cases, a single parameter name can apply to multiple paths through the slice, and can have different values for each path.