When R is High, all other inputs are overridden and the data output (Q) is driven Low on the active clock transition. This signal is available in the FDRE component. The FDRE flip-flop is also cleared by default on power-up.
When R is High, all other inputs are overridden and the data output (Q) is driven Low on the active clock transition. This signal is available in the FDRE component. The FDRE flip-flop is also cleared by default on power-up.