The cascadable 32-bit shift register implements any static length mode shift register without the dedicated multiplexers (F7AMUX, F7BMUX, and F8MUX). The following figure illustrates a 72-bit shift register. Only the last SRLC32E primitive needs to have its address inputs tied to 0b00111. Alternatively, shift register length can be limited to 71 bits (address tied to 0b00110) and a flip-flop can be used as the last register. (In an SRLC32E primitive, the shift register length is the address input + 1).
Figure 1. Example Static-Length Shift Register
