Slice SRL Timing Parameters - UG474

7 Series FPGAs Configurable Logic Block User Guide (UG474)

Document ID: UG474
Release Date: 2025-04-01
Revision: 1.9 English

The following table shows the SLICEM SRL timing parameters for a majority of the paths in Figure 1.

Table 1. Slice SRL Timing Parameters
Parameter	Function	Description
Sequential Delays for a Slice LUT Configured as an SRL
T_REG ⁽¹⁾	CLK to A/B/C/D outputs	Time after the CLK of a write operation that the data written to the SRL is stable on the A/B/C/D outputs of the slice.
T_REG (T_{REG_MUX})⁽¹⁾	CLK to AMUX - DMUX outputs	Time after the CLK of a write operation that the data written to the SRL is stable on the AMUX/BMUX/CMUX/DMUX outputs of the slice.
T_REG (T_{REG_M31})	CLK to DMUX output via MC31 output	Time after the CLK of a write operation that the data written to the SRL is stable on the DMUX output via MC31 output.
Setup and Hold Times for a Slice LUT Configured as an SRL⁽²⁾
T_CECK/T_CKCE(T_{CECK_SHFREG}/T_CKCESHFREG)	CE input (CE)	Time before/after the clock that the clock-enable signal must be stable at the CE input of the slice LUT (configured as an SRL).
T_WS/T_WH(T_{WS_SHFREG}/T_{WH_SHFREG})	CE input (WE)	Time before/after the clock that the write-enable signal must be stable at the WE input of the slice LUT (configured as an SRL).
T_DS/T_DH(3) (T_{DS_SHFREG}/T_{DH_SHFREG})	AI/BI/CI/DI configured as data inputs (DI)	Time before/after the clock that the data must be stable at the AI/BI/CI/DI inputs of the slice (configured as an SRL).
Clock CLK
T_MPW		Minimum clock pulse width for distributed RAM.
This parameter includes a LUT configured as a two-bit shift register. TXS = Setup Time (before clock edge), and TXH = Hold Time (after clock edge). Parameter includes AX/BX/CX/DX configured as a data input (DI2) or two bits with a common shift.