Slice SRL Timing Characteristics - UG474

The following figure illustrates the timing characteristics of a shift register implemented in a 7 series FPGA slice (a LUT configured as an SRL).

Figure 1. Slice SRL Timing Characteristics

Clock Event 1: Shift In

During a write (Shift In) operation, the single-bit content of the register at the address on the A/B/C/D inputs is changed, as data is shifted through the SRL. The data written to this register is reflected on the A/B/C/D outputs synchronously, if the address is unchanged during the clock event. If the A/B/C/D inputs are changed during a clock event, the value of the data at the addressable output (A/B/C/D outputs) is invalid.

• At time TWS before clock event 1, the write-enable signal (WE) becomes valid-High, enabling the SRL for the Write operation that follows.
• At time TDS before clock event 1, the data becomes valid (0) at the DI input of the SRL and is reflected on the A/B/C/D output after a delay of length TREG after clock event 1. Because address 0 is specified at clock event 1, the data on the DI input is reflected at A/B/C/D output, because it is written to register 0.

Clock Event 2: Shift In

• At time TDS before clock event 2, the data becomes valid (1) at the DI input of the SRL and is reflected on the A/B/C/D output after a delay of length TREG after clock event 2. Because address 0 is still specified at clock event 2, the data on the DI input is reflected at the D output, because it is written to register 0.

Clock Event 3: Shift In/Addressable (Asynchronous) Read

All Read operations are asynchronous to the CLK signal. If the address is changed (between clock events), the contents of the register at that address are reflected at the addressable output (A/B/C/D outputs) after a delay of length T_ILO (propagation delay through a LUT).

• At time T_DS before clock event 3, the data becomes valid (1) at the DI input of the SRL and is reflected on the A/B/C/D output T_REG time after clock event 3.
• The address is changed (from 0 to 2). The value stored in register 2 at this time is a 0 (in this example, this was the first data shifted in), and it is reflected on the A/B/C/D output after a delay of length T_ILO.

Clock Event 32: MSB (Most Significant Bit) Changes

At time T_REG after clock event 32, the first bit shifted into the SRL becomes valid (logical 0 in this case) on the DMUX output of the slice via the MC31 output of LUT A (SRL). This is also applicable to the AMUX, BMUX, CMUX, DMUX, and COUT outputs at time T_REG after clock event 1.