Slice Multiplexer Timing Parameters

Slice Multiplexer Timing Parameters - UG474

7 Series FPGAs Configurable Logic Block User Guide (UG474)

Document ID

UG474

Release Date

2025-04-01

Revision

1.9 English

The following table shows the slice multiplexer timing parameters for a majority of the paths in Figure 1 and Figure 2. Many of these parameter names are also used for paths that do not include the wide multiplexers.

Table 1. Slice Multiplexer Timing Parameters
Parameter	Function	Description
Propagation Delays for Slice Using the Wide Multiplexers
T_AXA/T_AXB/ T_BXB/ T_CXB/T_CXC	AX/BX/CX inputs to AMUX/BMUX/CMUX outputs	Propagation delay from the AX/BX/CX inputs of the slice through the select inputs of the multiplexers to the AMUX/BMUX/CMUX outputs of the slice.
T_OPAB/ T_OPBA/T_OPBB/ T_OPCB/ T_OPDB/ T_OPDC	A/B/C/D inputs to AMUX/BMUX/CMUX outputs	Propagation delay from the A/B/C/D LUT inputs of the slice through the multiplexers to the AMUX/BMUX/CMUX outputs of the slice.
T_{ILO_2}	A/C inputs to AMUX/CMUX outputs	Propagation delay from the A LUT inputs of the slice through the F7AMUX multiplexer to the AMUX output of the slice, or propagation delay from the C LUT inputs of the slice through the F7BMUX multiplexer to the CMUX output of the slice.