Slice Carry-Chain Timing Parameters - UG474

7 Series FPGAs Configurable Logic Block User Guide (UG474)

Document ID
UG474
Release Date
2025-04-01
Revision
1.9 English

The following table shows the slice carry-chain timing parameters for a majority of the paths in Figure 1.

Table 1. Slice Carry-Chain Timing Parameters
Parameter Function Description
Propagation Delays for Slice Configured as a Carry Chain

TAXA/TAXB/TAXC/TAXD/

TBXB/TBXC/TBXD/

TCXC/TCXD/

TDXD

AX/BX/CX/DX inputs to AMUX/BMUX/ CMUX/DMUX outputs Propagation delay from the AX/BX/CX/DX inputs of the slice through the carry logic to the AMUX/BMUX/CMUX/DMUX outputs of the slice.
TAXCY/TBXCY/TCXCY/TDXCY AX/BX/CX/DX inputs to COUT output Propagation delay from the AX/BX/CX/DX inputs of the slice to the COUT output of the slice.
TBYP CIN input to COUT output Propagation delay from the CIN input of the slice to the COUT output of the slice.
TOPCYA/TOPCYB/TOPCYC/ TOPCYD A/B/C/D inputs to COUT output Propagation delay from the A/B/C/D LUT inputs of the slice to the COUT output of the slice.
TCINA/TCINB/TCINC/TCIND CIN input to AMUX/BMUX/ CMUX/DMUX outputs Propagation delay from the CIN input of the slice to AMUX/BMUX/CMUX/DMUX outputs of the slice using XOR (sum).
Setup and Hold Times for a Slice Configured as a Carry Chain(1)
TCINCK/TCKCIN CIN input Time before/after the CLK that the CIN input of the slice must be stable.
  1. TXXCK = Setup Time (before clock edge), and TCKXX = Hold Time (after clock edge).