The following figure illustrates the timing characteristics of a slice carry chain implemented in a 7 series FPGA slice.
Figure 1. Slice Carry-Chain Timing Characteristics
Note: At time TCINCK before clock event 1, data from
the CIN input becomes valid-High at the Data input of the slice register. This is
reflected on any of the AQ/BQ/CQ/DQ pins at time TCKO after clock event
1.