A SLICEM function generator can also be configured as a 32-bit shift register without using the flip-flops available in a slice. Used in this way, each LUT can delay serial data from 1 to 32 clock cycles. The shiftin D (DI1 LUT pin) and shiftout Q31 (MC31 LUT pin) lines cascade LUTs to form larger shift registers. The four LUTs in a SLICEM are thus cascaded to produce delays up to 128 clock cycles. It is also possible to combine shift registers across more than one SLICEM. There are no direct connections between slices to form longer shift registers, nor is the MC31 output at LUT B/C/D available. The resulting programmable delays can be used to balance the timing of data pipelines.
Applications for shift registers include:
- Delay or latency compensation
- Synchronous FIFO and content addressable memory (CAM)
Shift register functions include:
- Write operation
- Synchronous with a clock input (CLK) and an optional clock enable (CE)
- Fixed read access to Q31
- Dynamic read access
- Performed through the 5-bit address bus, A[4:0]
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The LSB of the LUT address is unused and the software automatically ties it to a logic High.
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- Performed through the 5-bit address bus, A[4:0]
- Any of the 32 bits can be read out asynchronously (at the O6 LUT outputs, referred to as Q on the primitive) by varying the address
- This capability is useful in creating smaller shift registers (less than 32
bits).
- For example, when building a 13-bit shift register, set the address to the 13th bit.
- A storage element or flip-flop is available to implement a synchronous read.
- The clock-to-out of the flip-flop determines the overall delay and improves performance.
- However, one additional cycle of clock latency is added.
- Set or reset of the shift register is not supported.
Figure 1 is a logic block diagram of a 32-bit shift register.
Figure 2 illustrates an example shift register configuration occupying one function generator.
Figure 3 shows two 16-bit shift registers. The example shown can be implemented in a single LUT. For more information on the SRLC32E and SRL16E primitives, see Vivado Design Suite 7 Series FPGA and Zynq 7000 SoC Libraries Guide (UG953).
As mentioned earlier, the MC31 output and a dedicated connection between shift registers allows connecting the last bit of one shift register to the first bit of the next, without using the LUT O6 output. Longer shift registers can be built with dynamic access to any bit in the chain. The shift register chaining and the F7AMUX, F7BMUX, and F8MUX multiplexers allow up to a 128-bit shift register with addressable access to be implemented in one SLICEM. Figure 4 through Figure 6 illustrate various example shift register configurations that can occupy one SLICEM.
It is possible to create shift registers longer than 128 bits across more than one SLICEM. However, there are no direct connections between slices to form these shift registers.