Here is a summary of the shift registers:
- A shift operation requires one clock edge
- Dynamic-length read operations to the Q output of the LUT are asynchronous
- Static-length read operations to the Q output of the LUT are synchronous
- The data input has a setup-to-clock timing specification
- In a cascadable configuration, the Q31 output always contains the last bit value
- The Q31 output changes synchronously after each shift operation