Shift Operation
Figure 1 shows a timing diagram of the shift operation. The shift operation has these characteristics:
- Operates on a single clock edge
- Enabled by an active-High clock enable
- The input (D) is loaded into the first bit of the shift register
- Each bit is also shifted to the next highest bit position
- In a cascadable shift register configuration, the last bit is shifted out on the MC31 output
- The bit selected by the 5-bit address port (A[4:0]) appears on the Q output
Dynamic Read Operation
In a dynamic read operation:
- The Q output is determined by the 5-bit address
- Each time a new address is applied to the 5-input address pins, the new bit position value is available on the Q output after the time delay to access the LUT
- This operation is asynchronous and independent of the clock and clock-enable signals
Static Read Operation
In a static read operation:
- If the 5-bit address is fixed, the Q output always uses the same bit position
- This mode implements any shift-register length from 1 to 32 bits in one LUT
- The shift register length is (N + 1), where N is the input address (0–31)
- The Q output changes synchronously with each shift operation
- The previous bit is shifted to the next position and appears on the Q output