Revision History - UG474

7 Series FPGAs Configurable Logic Block User Guide (UG474)
Document ID
UG474
Release Date
2025-04-01
Revision
1.9 English

The following table shows the revision history for this document.

Section Revision Summary
04/01/2025 Version 1.9
Address Collision Added section.
09/27/2016 Version 1.8
7 Series FPGA CLB Resources Added Spartan 7 device family (updated Preface and added Table 1). Added Artix 7 7A12T and 7A25T devices to Table 2.
11/17/2014 Version 1.7
7 Series FPGA CLB Resources Updated Table 1 for new Artix 7 7A15T device.
08/11/2014 Version 1.6
7 Series FPGA CLB Resources Revised footnotes in Table 1 through Table 3.
Control Signals Revised polarity from independent to programmable.
Distributed RAM (SLICEM Only)
  • Added Primitive column to Table 1 and removed footnotes.
  • Renamed or made minor revisions to Figure 1 through Figure 9.
Clock – WCLK, Clock – CLK, Clock - C Revised sections.
08/6/2013 Version 1.5
General updates Added Artix 7 devices. Updated references to implementation tools.
11/05/2012 Version 1.4
General Timing Characteristics Changed “TCEO” to “TCECK” in Figure 1 and first bullet under General Timing Characteristics.
7 Series CLB Features Changed “uniformity” to “optimized” in last bullet.
Device Resources Changed “unified” to “scalable” in first sentence.
7 Series CLB Features
  • Deleted 7A350T device from Table 2.
  • Deleted 7V1500T and 7VH290T devices from Table 3.
Distributed RAM (SLICEM Only) Added reference to 7 Series FPGA Libraries Guide.
Shift Registers (SLICEM Only)
Flip-Flop Primitives
General Timing Characteristics Changed “TCEO” to “TCECK” in Figure 1 and first bullet.
01/30/2012 Version 1.3
7 Series FPGA CLB Resources Revised Table 1.
Distributed RAM (SLICEM Only) Added fifth paragraph.
Global Controls GSR and GTS Clarified last paragraph.
09/30/2011 Version 1.2
7 Series CLB Features Added last sentence under 7 Series CLB Features.
7 Series FPGA CLB Resources
CLB Arrangement Added first sentence under CLB Arrangement.
ASMBL Architecture Added section.
CLB Slices Added heading.
Carry Logic Added last paragraph.
Using Carry Logic Added last sentence.
Slice Multiplexer Timing Parameters
  • Added second sentence.
  • Modified Table 1.
Distributed RAM Timing Parameters Updated Table 1 for clarity.
Slice SRL Timing Parameters Updated Table 1 for clarity.
Devices Using Stacked Silicon Interconnect (SSI) Technology Added section.
03/28/2011 Version 1.1
7 Series FPGA CLB Resources Added devices XC7K355T, XC7K420T, and XC7K480T to Table 2. Portions of the text have been revised for clarity.
03/01/2011 Version 1.0
Initial release. N/A