Recommended Design Flow - UG474

CLB resources are inferred for generic design logic and do not require instantiation. Good HDL design is sufficient. A few items to note:

• CLB flip-flops have either a set or a reset. The designer must not use both set and reset.

• Flip-flops are abundant. Pipelining should be considered to improve performance.
• Control inputs are shared across a slice or CLB. The number of unique control inputs required for a design should be minimized. Control inputs include clock, clock enable, set/reset, and write enable.
• A 6-input LUT can be used as a 32-bit shift register for efficient implementation.
• A 6-input LUT can be used as a 64 x 1 memory for small storage requirements.
• Dedicated carry logic implements arithmetic functions effectively.

These steps indicate the recommended design flow:

1. Implement the design using preferred methodologies (HDL, IP, etc.).
2. Evaluate utilization reports to determine resources used.
3. Check to make sure arithmetic logic, distributed RAM, and SRL are used, when helpful.
4. Consider flip-flop usage.
5. Pipeline for performance
6. Use dedicated flip-flops at the outputs of dedicated resources (block RAM, DSP)
7. Allow shift registers to use SRL (avoid set/resets)
8. Minimize the use of set/resets.