Although the use of most resources affects the resulting device pinout, CLB usage has little effect on pinouts because they are distributed throughout the device. The ASMBL architecture provides maximum flexibility with CLBs on both sides of most I/Os.
The best approach is to let the tools choose the I/O locations based on the FPGA requirements. Results can be adjusted if necessary for board layout considerations. The timing constraints should be set so that the tools can choose optimal placement for the design requirements.
Carry logic cascades vertically up a column, so wide arithmetic buses might drive a vertical orientation to other logic, including I/O.
While most 7 series devices are available in flip-chip packages, taking full advantage of the distributed I/O in the ASMBL architecture, the smaller devices are available in wire-bond packages at a lower cost. In these packages, some pins are naturally closer to the I/Os and special resources than others, so pin placement should be done after the internal logic is defined.