Multiplexer Primitives - UG474

7 Series FPGAs Configurable Logic Block User Guide (UG474)

Document ID
UG474
Release Date
2025-04-01
Revision
1.9 English

The multiplexer primitives provide direct instantiation of the dedicated multiplexers in each slice, allowing wider multiplexers to be built. The following table describes the two primitives.

Table 1. Multiplexer Primitives
Primitive Inputs Resource Output Function
MUXF7

LUT outputs

(4:1 multiplexer)

F7AMUX or F7BMUX 8:1 multiplexer
MUXF8 F7AMUX and F7BMUX outputs (8:1 multiplexer) F8MUX 16:1 multiplexer

The port signals are the same for both multiplexer primitives. The following figure shows MUXF7.

Figure 1. MUXF7 Primitive

Port Signals

Data In - I0, I1

The data input provides the data to be selected by the select signal (S).

Control In - S

The select input signal determines the data input signal to be connected to the output O. Logic 0 selects the I0 input, while logic 1 selects the I1 input.

Data Out - O

The data output O provides the data value (one bit) selected by the control inputs.